The present invention relates to a synchronous semiconductor storage device whose internal circuit operates in synchronization with a system clock.
Conventionally, as a synchronous semiconductor storage device, there is a synchronous masked ROM that operates at a system clock of 100 MHz according to the control timing shown in FIGS. 13A through 13I. In this synchronous masked ROM (referred to as a `synchronous MROM` hereinafter), a word line is made to rise, or turned on after the input of a row address, and a desired column selector is enabled after the input of a column address shown in FIG. 13B, to charge selected bit lines 1 and 2 shown in FIGS. 13E and 13H and a virtual GND line up to a precharge level on the basis of precharging timings 1 and 2 shown in FIGS. 13C and 13G, respectively (the first and second stages in two cycles). Next, in each cycle, the bit line sensing, or the bit line drawing by the selected memory cell, is performed (the third stage). Next, a potential difference between the bit line and a reference line is amplified by a sense amplifier when the sense amplifier enabling signal SAE1, SAE2 (shown in FIGS. 13D and 13I) has an H-level (the fourth stage). Finally, data CA0, CA1, . . . shown in FIG. 13F are sequentially output (the fifth stage). The CAS latency in this case is five. The term `CAS latency` means the number of cycles of a clock CK (shown in FIG. 13A) from the input of a column address that is an input command, to the output of read data.
As described above, in the aforementioned synchronous MROM, the memory cell reading operation and the precharge operation of the bit line and the virtual GND line are independently executed.
According to the control timing of the synchronous MROM, five clock pulses are necessary during the time from the column address input to the read data output (namely, CAS latency: 5). In contrast to this, the operation of a synchronous dynamic RAM (referred to as a `synchronous DRAM` hereinafter) has a CAS latency of 2 or 3 from the column address input to the read data output when the system clock of 100 MHz is used. That is, in the synchronous DRAM, the read data is output in 20 ns or 30 ns from the column address input. In contrast to this, the synchronous MROM generally has a CAS latency of 5 (or 6) from the column address input to the read data output when the system clock of 100 MHz is used. That is, in the synchronous MROM, the read data is output in 50 ns (or 60 ns) from the column address input.
As described above, the synchronous MROM, in which the memory cell read operation and the precharge operation of the bit lines and the virtual GND line are independently executed, has a CAS latency of 5, meaning that the access becomes slower than that of the synchronous DRAM. Therefore, in a system using both the synchronous MROM and the synchronous DRAM, system performance disadvantageously deteriorates by the synchronous MROM that has a longer access time.